The present invention pertains to systems and methods for improving the deposition of conformal copper seed layers in integrated circuit metalization. The invention involves controlling the morphology of the barrier layer deposited underneath the copper seed layer. The barrier layer can be composed of TaN and Ta, or TaN alone. It can also be composed of TiN or TiNSi. The process conditions of the barrier layer deposition are carried out in a manner that results in a highly or completely amorphous crystalline structure. Such a barrier layer allows for conformal deposition of the copper seed layer on top of the barrier layer that is less susceptible to agglomeration.
Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it has not been used because of certain challenges it presents, including the fact that it readily diffuses into silicon oxide and degrades insulating electrical properties even at very low concentrations. Recently, however, IC manufacturers have been turning to copper because of its high conductivity and electromigration resistance, among other desirable properties. Most notable among the IC metalization processes that use copper is Damascene processing.
Damascene processing is a method for forming metal lines on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). A barrier layer that blocks diffusion of copper atoms is formed over the dielectric layer topology. Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching.
In a typical copper IC process, the formation of the desired conductive wires on the chip generally begins with a seed layer, usually deposited by physical vapor deposition (PVD). The seed layer provides a conformal, conductive layer on which a thicker layer of copper is electrofilled in order to fill in the features (e.g., trenches and vias) of the semiconductor wafer. PVD has traditionally been used to form the seed layer, but does not always provide totally conformal step coverage, particularly with respect to surface features with high aspect ratios (greater than about 5:1), where aspect ratio refers to the ratio of the feature height to the feature width. Coverage that is not conformal means coverage that is uneven, i.e., thicker in some places than others, and that may include actual gaps where the metal is discontinuous, all of which are highly undesirable in IC manufacturing. Modern integrated circuit manufacturing has moved toward features with these high-aspect ratios, particularly in advanced integrated circuits where copper is used at the conductive metal, e.g., Damascene processing. For instance, a typical via may have a diameter of 0.07 xcexcm (the width of 266 copper atoms) but have a depth of 0.4 xcexcm, which is an aspect ratio of 5.7:1.
A major and unresolved problem of copper metalization is the inability to guarantee conformal deposition of the copper. For instance, the copper tends to agglomerate. It also tends to form notches at the top of surface features. Notching is a phenomenon that occurs at the top edge of a feature, wherein the changing crystalline orientation interferes with conformal deposition, so that a thinly deposited or even void region develops at the top of the feature.
Typically, an integrated circuit substrate is coated with a barrier layer that blocks diffusion of copper atoms. It is typically formed over the dielectric layer and prior to deposition of copper. The problems of agglomeration and notching of the copper are in large part due to how the copper interacts with this barrier layer. What is therefore needed is a way to form the barrier layer that reduces or eliminates agglomeration and notching of the copper.
The present invention pertains to systems and methods for improving the deposition of conformal copper seed layers in integrated circuit metalization. The invention involves controlling the morphology of the barrier layer deposited underneath the copper seed layer. The barrier layer can be composed of TaN and Ta, or TaN alone. It can also be composed of TiN or TiNSi. The process conditions of the barrier layer deposition are carried out in a manner that results in a highly or completely amorphous crystalline structure. Such a barrier layer allows for conformal deposition of the copper seed layer on top of the barrier layer that is less susceptible to agglomeration.
One aspect of the present invention provides a method for forming a barrier layer comprising tantalum nitride by physical vapor deposition on a semiconductor substrate, such that the barrier layer reduces agglomeration and notching of a copper seed layer formed on top of the barrier layer. The method includes sputtering a target comprising tantalum and introducing a nitrogen source in an amount so that the surface of the barrier layer displays a randomness greater than about 50%. The nitrogen source is typically N2 gas, flowed at about 10 to 110 SCCM. The method may be carried out at 2 to 8 millitorr and about 20 to 80xc2x0 C. The barrier layer may be deposited at about 1 to 15 xc3x85 per second. The barrier layer may be deposited to a thickness of about 25 to 100 xc3x85 as measured at the bottom of a feature on the semiconductor substrate.
Randomness in a sample can be seen in an X-ray diffraction (XRD) plot. Samples with completely-ordered crystalline structures (0% random) ideally have XRD peaks that have a maximal intensity and zero width, though in reality peaks that represent highly-ordered structures are not perfectly sharp, but merely very sharp and narrow. A purely random sample (100% random) has no discernable peaks. Randomness is typically quantified as a percentage number determined from another plot known as an XRD Rocking curve.
Another aspect of the present invention provides a method for forming a barrier layer comprising tantalum and tantalum nitride by physical vapor deposition on a semiconductor substrate, such that the barrier layer reduces agglomeration and notching of a copper seed layer formed on top of the barrier layer. The method includes sputtering a target comprising tantalum, and sputtering a target comprising tantalum while introducing a nitrogen source to deposit tantalum nitride at the surface of the barrier layer in an amount so that the surface of the barrier layer displays a randomness greater than about 50%. The nitrogen source is typically N2 gas, flowed at about 10 to 110 SCCM. The method may be carried out at 2 to 8 millitorr and about 20 to 80xc2x0 C. The barrier layer may be deposited at about 1 to 15 xc3x85 per second. The tantalum nitride layer may be deposited to a thickness of about 25 to 100 xc3x85 as measured at the bottom of a feature on the semiconductor substrate. The tantalum layer may be deposited to a thickness of about 25 to 150 xc3x85.
Another aspect of the present invention provides a method for forming a barrier layer comprising tantalum and tantalum nitride by physical vapor deposition on a semiconductor substrate, such that the barrier layer reduces agglomeration and notching of a copper seed layer formed on top of the barrier layer. The method includes sputtering a target comprising tantalum while introducing a nitrogen source to deposit tantalum nitride as a bottom layer, sputtering a target comprising tantalum, and sputtering a target comprising tantalum to deposit a tantalum middle layer, and sputtering a target comprising tantalum while introducing a nitrogen source to deposit tantalum nitride as a top layer at the surface of the barrier layer in an amount so that the surface of the barrier layer displays a randomness greater than about 50%. The nitrogen source is typically N2 gas. The method may be carried out at 2 to 8 millitorr and about 20 to 80xc2x0 C. The barrier layer may be deposited at about 1 to 15 xc3x85 per second. Both tantalum nitride layers may be deposited to a thickness of about 25 to 100 xc3x85 as measured at the bottom of a feature on the semiconductor substrate. The tantalum layer may be deposited to a thickness of about 25 to 150 xc3x85.
Another aspect of the present invention provides a method for forming a barrier layer comprising titanium nitride by chemical vapor deposition on a semiconductor substrate, such that the barrier layer reduces agglomeration and notching of a copper seed layer formed on top of the barrier layer. The method includes introducing a titanium-containing precursor and a nitrogen source into a chamber, the nitrogen source being introduced in an amount so that the surface displays a randomness of at least about 50%.
The titanium-containing precursor may be TDEAT. The nitrogen source may be NH3. The method may be carried out at about 25 to 100 torr. The method of claim 45 wherein the method may be carried out at about 200 to 500xc2x0 C. The NH3 flow may be about 3 to 8 liters gas per minute. The TDEAT flow may be about 0.02 to 0.20 mg liquid per minute. The barrier layer may be deposited at about 1 to 15 xc3x85 per second. Both tantalum nitride layers may be deposited to a thickness of about 25 to 100 xc3x85 as measured at the bottom of a feature on the semiconductor substrate.
Another aspect of the invention provides for an apparatus module for physical vapor deposition of a barrier layer comprising tantalum nitride in a manner that the surface of the barrier layer displays a randomness greater than about 50%. The apparatus includes a physical deposition chamber, a tantalum target, a source of neutral sputtering gas and a nitrogen source. The nitrogen source is typically N2 gas. The apparatus may have a substrate having a dielectric patterned for Damascene processing.
Another aspect of the invention provides for an apparatus module for chemical vapor deposition of a barrier layer comprising tantalum nitride in a manner that the surface of the barrier layer displays a randomness greater than about 50%. The apparatus includes a chemical deposition chamber, a source of a titanium-containing precursor and a nitrogen source. The nitrogen source can be NH3. The apparatus may have a substrate having a dielectric patterned for Damascene processing. The titanium-containing precursor may be TDEAT.
Another aspect of the invention provides for a partially fabricated integrated circuit comprising a via or trench and a barrier layer lining the via or trench and including tantalum nitride, wherein the barrier layer displays a randomness of at least about 50%. The barrier layer reduces agglomeration and notching of a copper seed layer deposited on the barrier layer. The barrier layer may be 25 to 100 xc3x85 thick at the bottom of a feature of the semiconductor substrate. The barrier layer may further comprises at least one layer of tantalum.
Another aspect of the invention provides for a partially fabricated integrated circuit comprising a via or trench and a barrier layer lining the via or trench and including titanium nitride, wherein the barrier layer displays a randomness of at least about 50%. The barrier layer reduces agglomeration and notching of a copper seed layer deposited on the barrier layer. The barrier layer may be 25 to 100 xc3x85 thick at the bottom of a feature of the semiconductor substrate.
These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.